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Logic analyzer (HP 1631D) ID:19: Difference between revisions
Logic analyzer (HP 1631D) ID:19 (view source)
Revision as of 02:02, 10 November 2016
, 10 November 2016Updated template names
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<!--43× 25 MHz state + 16× 100 MHz timing + 2× 50 MHz analog channels--> | <!--Information to be added to Specs: 43× 25 MHz state + 16× 100 MHz timing + 2× 50 MHz analog channels--> | ||
{{ | {{Equipment page | ||
|toolname=Logic Analyser | |toolname=Logic Analyser | ||
|model=HP 1631D | |model=HP 1631D | ||